The present invention relates generally to semiconductor device manufacturing techniques and, more particularly, to an improved double patterning process for integrated circuit (IC) device manufacturing.
Double exposure, double etch patterning has been adopted in 32 nanometer (nm) node to improve pattern density at critical levels. Double patterning is a process for obtaining designed layout patterns, by distributing layout patterns into a plurality of masks and performing a plurality of exposure processes, etching processes and the like. When the distance between two layout patterns is small, if the two layout patterns are formed on an identical mask, the two layout patterns cannot separately be formed on a wafer. Double patterning is therefore used to avoid such a problem.
More specifically, a first exposure of photoresist is used to transfer a first pattern to an underlying hardmask layer by etching. After the photoresist is removed following the hardmask pattern transfer, a second layer of photoresist is then coated onto the once-etched hardmask layer. This second photoresist layer undergoes a second exposure, imaging additional features (by etching) in between the features already patterned in the hardmask layer. The resulting surface pattern of first and second features in the patterned hardmask can then be transferred into a layer beneath the hardmask, such as a dielectric layer or a gate electrode layer, for example. This effectively allows for a doubling of feature density.
However, there are issues related to the double patterning technique. In particular, one obstacle relates to the topography formed in a layer (e.g., a hardmask) as a result of the first patterning and etch process. The resulting topography from a first patterning process reduces the lithography process window for the second patterning process. This is especially a problem for high numerical aperture (NA) lithography due to its extremely shallow depth of focus.